The testing of integrated circuits presents many challenges owing to the extremely small dimensions of the circuit elements and the nets connecting them. The problem is further aggravated by the fact that several of the internal nets and nodes of the circuit are embedded in inner layers of the interconnect. The transient response of internal circuit nets is an important parameter in analyzing the transient behaviour of the circuit. The measurement of the transient response requires the measurement of the voltage at the selected node at various instants of time in response to a step change in applied voltage at a selected point in the circuit.
At present, the voltage at any embedded net is probed using:                An ebeam machine. This method suffers from the following limitations:        Absolute Voltage Measurement is not possible        Nets need to propogate until Top metal.        Cannot be used for a large number of nets owing to excessive m/c setup time and manual effort requirements.        Tapping the node to a pad and then probing with an oscilloscope. This method also suffers from the following limitations:        Probing the internal node and bringing it to the pad is costly as it changes the inherent charateristic of the net and disturbs its electrical behaviour.        It is often not possible to bring the net outside due to either layout density or pad limitations.        This technique needs extra pads/Machine setup.        
A methodology is therefore needed to probe embedded nets. Such a methodology would be immensely useful in designing/testing/debugging/characterization of a time dependent design. Such methodology will also be helpful in providing a correlation between simulation and Silicon, which will aid model development.